Top 3 Verilog zipcpu Projects
A small, light weight, RISC CPU soft coreProject mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
An Open Source configuration of the Arty platformProject mention: FPGA and Simulation tools for Risc-V design | reddit.com/r/FPGA | 2020-12-24
I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).
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A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systemsProject mention: How do you successfully compile a working verilator package on Ubuntu? | reddit.com/r/ZipCPU | 2021-07-27
Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.