Verilog Verilog

Open-source Verilog projects categorized as Verilog | Edit details

Top 19 Verilog Verilog Projects

  • GitHub repo darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | | 2021-06-26

    Just found whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.

  • GitHub repo hdl

    HDL libraries and projects

    Project mention: Intel Quartus Version Control? | | 2021-02-21

    There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus.

  • Scout APM

    Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.

  • GitHub repo zipcpu

    A small, light weight, RISC CPU soft core

    Project mention: What modules/hardware would you like to see? | | 2021-05-14

    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.

  • GitHub repo open-fpga-verilog-tutorial

    Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

    Project mention: What's the difference between FPGA, RISC-V, Arduino? | | 2021-04-22

    Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.

  • GitHub repo openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Project mention: Resources for a physical design engineer | | 2021-07-20

    Specifically openlane ( is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter

  • GitHub repo biriscv

    32-bit Superscalar RISC-V CPU

    Project mention: BiRISC-V – 32-bit Superscalar RISC-V CPU | | 2021-07-20
  • GitHub repo wbuart32

    A simple, basic, formally verified UART controller

    Project mention: How can I get Verilator to Prompt for User Input? | | 2021-04-19

    The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  • GitHub repo cpu11

    Revengineered ancient PDP-11 CPUs, originals and clones

    Project mention: I finally got a PDP-8i (sort of). | | 2021-04-12

    There are quite a few HDL implementations, eg CPU11 and this list.

  • GitHub repo vgasim

    A Video display simulator

    Project mention: More thorough resources for Verilator | | 2021-07-14

    Yes--I've done that with both VGA and HDMI. You can find the example here if you want to see how I did it.

  • GitHub repo Haasoscope

    Docs, design, firmware, and software for the Haasoscope

    Project mention: Hello world! On electric😎 finished solder Chinese oscilloscope | | 2021-07-10

    I was thinking of getting one of those to build myself but i might go for a haasoscope instead. I need a scope to be able to read the analog signals from a ym2612 chip and i believe i need a high speed one for it.

  • GitHub repo sdspi

    SD-Card controller, using a SPI interface that is (optionally) shared

    Project mention: SoC FPGA design to ASIC | | 2021-07-22

    How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.

  • GitHub repo wbscope

    A wishbone controlled scope for FPGA's

    Project mention: Working with FPGAs (Questions) | | 2021-07-10

    One of my first projects on my own was a design that allowed me to interact with a bus from an external UART. I then built my own internal logic analyzer. From these humble beginnings, I fairly well insulated myself from the vendor architectures out there since I can do all of my design in Verilog.

  • GitHub repo dpll

    A collection of phase locked loop (PLL) related projects

    Project mention: Digital Loop Filter for Digital PLL Design | | 2021-01-25

    Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.

  • GitHub repo zbasic

    A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

    Project mention: How do you successfully compile a working verilator package on Ubuntu? | | 2021-07-27

    Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.

  • GitHub repo dbgbus

    A collection of debugging busses developed and presented at

    Project mention: Need help with Objcopy for Verilog Hex File | | 2021-07-07

    As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.

  • GitHub repo ice40_power

    Power analysis of the ICE40UP5K-SG48 devices

    Project mention: iCE40 power consumption question | | 2021-06-30

    You can probably extrapolate from the numbers here.

  • GitHub repo rapcores

    Robotic Application Processor

    Project mention: FPGA development automation practices | | 2021-07-21

    Our project is: I have a draft article about the tools we use, but it is several months old now. We are about one year into the project, and I am amazed how every month some new tooling seems to pop up that solves some problem.

  • GitHub repo Kiwi-Project-Samples

    Sample projects for the uLab Kiwi FPGA + ESP32, and the Kiwi Lite development boards

    Project mention: µLab Kiwi and Kiwi Lite FPGA+ESP32 Development boards on Crowd Supply | | 2021-07-18
  • GitHub repo SDRAM_Controller_Verilog

    This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-27.


What are some of the best open-source Verilog projects in Verilog? This list will help you:

Project Stars
1 darkriscv 1,153
2 hdl 802
3 zipcpu 703
4 open-fpga-verilog-tutorial 498
5 openlane 375
6 biriscv 273
7 wbuart32 144
8 cpu11 102
9 vgasim 96
10 Haasoscope 66
11 sdspi 54
12 wbscope 53
13 dpll 42
14 zbasic 29
15 dbgbus 19
16 ice40_power 10
17 rapcores 10
18 Kiwi-Project-Samples 4
19 SDRAM_Controller_Verilog 1