Top 19 Verilog Verilog Projects
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!Project mention: Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux | reddit.com/r/linux | 2021-06-26
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
HDL libraries and projectsProject mention: Intel Quartus Version Control? | reddit.com/r/FPGA | 2021-02-21
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.
A small, light weight, RISC CPU soft coreProject mention: What modules/hardware would you like to see? | reddit.com/r/FPGA | 2021-05-14
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
Learn how to design digital systems and synthesize them into an FPGA using only opensource toolsProject mention: What's the difference between FPGA, RISC-V, Arduino? | reddit.com/r/RISCV | 2021-04-22
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.Project mention: Resources for a physical design engineer | reddit.com/r/chipdesign | 2021-07-20
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
32-bit Superscalar RISC-V CPUProject mention: BiRISC-V – 32-bit Superscalar RISC-V CPU | news.ycombinator.com | 2021-07-20
A simple, basic, formally verified UART controllerProject mention: How can I get Verilator to Prompt for User Input? | reddit.com/r/FPGA | 2021-04-19
The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.
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Revengineered ancient PDP-11 CPUs, originals and clonesProject mention: I finally got a PDP-8i (sort of). | reddit.com/r/retrobattlestations | 2021-04-12
There are quite a few HDL implementations, eg CPU11 and this list.
A Video display simulatorProject mention: More thorough resources for Verilator | reddit.com/r/FPGA | 2021-07-14
Yes--I've done that with both VGA and HDMI. You can find the example here if you want to see how I did it.
Docs, design, firmware, and software for the HaasoscopeProject mention: Hello world! On electric😎 finished solder Chinese oscilloscope | reddit.com/r/electronics | 2021-07-10
I was thinking of getting one of those to build myself but i might go for a haasoscope instead. https://github.com/drandyhaas/Haasoscope I need a scope to be able to read the analog signals from a ym2612 chip and i believe i need a high speed one for it.
SD-Card controller, using a SPI interface that is (optionally) sharedProject mention: SoC FPGA design to ASIC | reddit.com/r/FPGA | 2021-07-22
How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.
A wishbone controlled scope for FPGA'sProject mention: Working with FPGAs (Questions) | reddit.com/r/FPGA | 2021-07-10
One of my first projects on my own was a design that allowed me to interact with a bus from an external UART. I then built my own internal logic analyzer. From these humble beginnings, I fairly well insulated myself from the vendor architectures out there since I can do all of my design in Verilog.
A collection of phase locked loop (PLL) related projectsProject mention: Digital Loop Filter for Digital PLL Design | reddit.com/r/chipdesign | 2021-01-25
Are you interested in an all-digital solution? If so, I have a couple of digital PLL's you might want to check out. These are the PLL's I use if I want to demodulate a digital signal in hardware, as demonstrated by this example. If what you are looking for is a mixed digital/analog solution, then ... I don't have an example.
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systemsProject mention: How do you successfully compile a working verilator package on Ubuntu? | reddit.com/r/ZipCPU | 2021-07-27
Let me also point out that I rarely use Verilators -exe flag. I tend instead to build my designs in steps: 1) Run Verilator, 2) run make -f Vtoplvl.mk in the obj_dir directory, 3) turn my test script into an object file, and only then 4) link everything together into an executable. I've also been known for peeking at Verilator's internal variables during a simulation run--but that may be another topic entirely.
A collection of debugging busses developed and presented at zipcpu.comProject mention: Need help with Objcopy for Verilog Hex File | reddit.com/r/FPGA | 2021-07-07
As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
Power analysis of the ICE40UP5K-SG48 devicesProject mention: iCE40 power consumption question | reddit.com/r/FPGA | 2021-06-30
You can probably extrapolate from the numbers here.
Robotic Application ProcessorProject mention: FPGA development automation practices | reddit.com/r/FPGA | 2021-07-21
Our project is: https://github.com/RAPcores/rapcores I have a draft article about the tools we use, but it is several months old now. We are about one year into the project, and I am amazed how every month some new tooling seems to pop up that solves some problem.
Sample projects for the uLab Kiwi FPGA + ESP32, and the Kiwi Lite development boardsProject mention: µLab Kiwi and Kiwi Lite FPGA+ESP32 Development boards on Crowd Supply | reddit.com/r/PrintedCircuitBoard | 2021-07-18
This SDRAM controller is for MT48LC32M16 SDRAM. This module was designed under the assumption that the clock rate is 100MHz.
What are some of the best open-source Verilog projects in Verilog? This list will help you: