Verilog Systemverilog

Open-source Verilog projects categorized as Systemverilog | Edit details

Verilog Systemverilog Projects

  • GitHub repo openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

    Project mention: Resources for a physical design engineer | | 2021-07-20

    Specifically openlane ( is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter

  • GitHub repo open-register-design-tool

    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

    Project mention: Thoughts about SystemRDL ? | | 2021-03-08

    I have used this compiler ( to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).

  • Scout APM

    Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2021-07-20.


Project Stars
1 openlane 375
2 open-register-design-tool 138