Verilog Systemverilog Projects
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.Project mention: Resources for a physical design engineer | reddit.com/r/chipdesign | 2021-07-20
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
Tool to generate register RTL, models, and docs using SystemRDL or JSpec inputProject mention: Thoughts about SystemRDL ? | reddit.com/r/FPGA | 2021-03-08
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
Scout APM: A developer's best friend. Try free for 14-days. Scout APM uses tracing logic that ties bottlenecks to source code so you know the exact line of code causing performance issues and can get back to building a great product faster.