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Mentions
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Stars | Project | Description |
|---|---|---|---|
| 14 | 2,349 | OpenTitan: Open source silicon root of trust | |
| 20 | 1,237 | Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. | |
| 15 | 1,049 | A Verilog synthesis flow for Minecraft redstone circuits | |
| 7 | 1,004 | Send video/audio over HDMI on an FPGA | |
| 3 | 920 | AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication | |
| 12 | 905 | RSD: RISC-V Out-of-Order Superscalar Processor | |
| 3 | 869 | CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform | |
| 2 | 775 | SCR1 is a high-quality open-source RISC-V MCU core in Verilog | |
| 8 | 773 | VeeR EH1 core | |
| 3 | 615 | Proving leftpad correct in a dozen different ways | |
| 1 | 581 | The root repo for lowRISC project and FPGA demos. | |
| 5 | 525 | A Linux-capable RISC-V multicore for and by the world | |
| 3 | 504 | Project F brings FPGAs to life with exciting open-source designs you can build on. | |
| 2 | 484 | OpenSource GPU, in Verilog, loosely based on RISC-V ISA | |
| 4 | 445 | BaseJump STL: A Standard Template Library for SystemVerilog | |
| 2 | 427 | Contains the code examples from The UVM Primer Book sorted by chapters. | |
| 1 | 361 | Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats. | |
| 2 | 332 | This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster. | |
| 5 | 295 | NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards | |
| 1 | 244 | Public repository for Litefury & Nitefury |
Popular SystemVerilog Topics
Latest Mentions
Latest mentioned SystemVerilog repos
| Stars | Project |
|---|---|
| 13 | ebrick-demo |
| 1 | PurdNyUart |
| 6 | GettingVerilatorStartedWithUVM |
| 56 | FazyRV |
| 1,004 | hdmi |
| 2,349 | opentitan |
| 61 | sargantana |
| 2 | petalinux_notes |
| 1 | RTLDesignSherpa |
| 34 | MacPlus_MiSTer |
| 105 | analogue-pocket-utils |
| 1,237 | ibex |
| 2 | ulm-on-ice |
| 1 | NeuralNetworkOnFPGA |
| 152 | Saturn_MiSTer |
| 784 | swerv_eh1 |
| 57 | cheriot-ibex |
| 3 | Verilog-SystemVerilog |
| 60 | CX |
| 525 | black-parrot |
Latest Discoveries
Latest discovered SystemVerilog repos
| Stars | Project |
|---|---|
| 13 | ebrick-demo |
| 6 | GettingVerilatorStartedWithUVM |
| 56 | FazyRV |
| 61 | sargantana |
| 2 | petalinux_notes |
| 1 | RTLDesignSherpa |
| 2 | ulm-on-ice |
| 1 | NeuralNetworkOnFPGA |
| 152 | Saturn_MiSTer |
| 57 | cheriot-ibex |
| 3 | Verilog-SystemVerilog |
| 60 | CX |
| 0 | osdr-q10 |
| 51 | fpga-gameandwatch |
| 4 | AI-Robotics |
| 1 | PurdNyUart |
| 5 | fpga_screensaver |
| 1 | VGA-SRAM |
| 31 | sigma_delta_converters |
| 2 | simple_ddr_ctrl |