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SystemVerilog Vhdl Projects
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as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.
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NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
The latest post mention was on 2023-01-12.
SystemVerilog Vhdl related posts
- A simple high-throughput open-source packet generator
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- ASIC roundup of open source RISC-V CPU cores
- Need help in CPU design
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Index
| Project | Stars | |
|---|---|---|
| 1 | ndk-app-minimal | 15 |
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