SystemVerilog Vhdl

Open-source SystemVerilog projects categorized as Vhdl

SystemVerilog Vhdl Projects

  • ndk-app-minimal

    Minimal Application based on Network Development Kit (NDK) for FPGA cards

    Project mention: A simple high-throughput open-source packet generator | /r/FPGA | 2023-01-12

    as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.

  • SonarQube

    Static code analysis for 29 languages.. Your projects are multi-language. So is SonarQube analysis. Find Bugs, Vulnerabilities, Security Hotspots, and Code Smells so you can release quality code every time. Get started analyzing your projects today for free.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2023-01-12.

SystemVerilog Vhdl related posts


Project Stars
1 ndk-app-minimal 15
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