C Rtl Projects
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and moreProject mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard  for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
The modern API for authentication & user identity. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
C Rtl related posts
Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
3 projects | news.ycombinator.com | 10 Dec 2023
A repository that tracks upstream but allows separate tracking.
1 project | /r/git | 3 Apr 2023
Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
7 projects | news.ycombinator.com | 3 Mar 2023
Chipyard: An Open Source RISC-V SoC Design Framework
1 project | news.ycombinator.com | 15 Dec 2021