zipcpu
verilog-axi
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zipcpu | verilog-axi | |
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13 | 9 | |
1,190 | 1,252 | |
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6.3 | 3.0 | |
about 1 month ago | 5 months ago | |
Verilog | Verilog | |
- | MIT License |
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zipcpu
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Xilinx FIFO generator for skid buffer?
For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
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Five legally free FPGA books (plus one about Machine Learning)
The Some Assembly Required series on Youtube has a good walkthrough of implementing a 6502, from scratch. Also, /u//ZipCPU has some good documentation of the CPU he built from scratch, as well as some tutorials, at https://zipcpu.com/ and https://github.com/ZipCPU/zipcpu.
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What make xilinx fpga runs soft core cpu faster than lattice
check out this usage chart for the ZipCPU's logic usage (also linked above). Each line in the chart beginning with Zip represents a different CPU configuration. If the FPGA speeds were the same (they aren't typically), then each configuration line should have the same CPU speed (not counting interconnect, RAM or peripherals). Two of the columns measure iCE40 4-LUTs and Xilinx 6-LUTs.
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OS AXI4 Crossbar with good performance
If you are looking for an AXI4 cache implementation, the ZipCPU currently supports two (I+D) that you might be able to gain some insights from. There's the AXI instruction cache implementation, and an AXI4 data cache implementation. They are both one way caches. Both were featured in an article on performance measurement last year. The data cache implementation doesn't support exclusive access yet--that's still on my to-do list. You can find these caches demonstrated in my AXI DMA check repo, if you'd like to try them out.
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Why is simulation such an important step in the design workflow? Why not just run on actual hardware?
My experience comes from both the ZipCPU (a basic pipelined CPU) and verifying a lot of bus components. I haven't (yet) done an out of order processor, although I will say that verifying a cache gets really basic with formal methods, and I've now verified several cache implementations. The first data cache I wrote took me about two weeks to both write and complete a full formal proof.
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What modules/hardware would you like to see?
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
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Using Xilinx AXI Datamover to move DDR memory to FPGA block RAM
Were this my task, I'd write the core myself. I have, for example, an AXI instruction cache you can reference if you'd like and I'm currently building a data cache following this Wishbone example, only for AXI instead. (I was hoping to offer a Zoom call today for anyone interested, where we'd try verifying this new data cache, but ... I didn't get far enough along on the project to do so today. Perhaps next week.()
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[Help] CPU: Changing from BRAM to real program flash
In some of my early CPU tests, one of my earlier instruction fetches would just keep reading up to 16 instructions ahead of time. I thought this was great until I started examining the resulting performance. The first problem was that it wouldn't release the bus for either a data load or store, and the next problem was that the request was so long the result was often irrelevant by the time it arrived since the CPU had already branched away from the addresses it was fetching.
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Can someone help me fix my simulation workflow?
That solution isn't all that satisfying to me, so ... I'm trying to do better. My next attempt is going to be 1) using the ZipCPU instead of the ARM (at least for simulation, and certainly instead of a BFM), 2) using AXI instead of Wishbone (Yes, the ZipCPU can now speak either Wishbone or (mostly) AXI), using my own AXI infrastructure (to get rid of the bridges), and using AutoFPGA to compose the design together and handle addressing requirements (instead of Qsys).
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Soft CPUs - how to debug and test in a sane way?
Yes, the ZipCPU is modular. It consists of several components: a pre-fetch (of which there are several to choose from), an instruction decoder, an ALU, a divide unit, a multiply unit, and a memory unit (of which there are multiple to choose from again). Each unit has its own unit tests (proofs--not simulations).
verilog-axi
- awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi
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Using Xilinx AXI interconnect to connect AXI lite master to AXI lite slaves
You can also use an AXI lite crossbar like this one: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axil_crossbar.v
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OS AXI4 Crossbar with good performance
does anybody knows some sort of AXI4 Crossbar or maybe even an Interconnect with good performance in terms of latency? If I have something like the following scenario, the idea is that M1 txns must have very low access latency in the sense of making the CPU capable of processing at least one instruction per cc. For M2 it's fine to take more time, but what I'm observing is that with this solution for instance, I cannot achieve constant fetching from the CPU, there's always a 1 cc delay between req/resp what hits bad my IPC. Also, S1 cannot be tightly coupled to the CPU because sometimes M2 might require to also fetch from IRAM/ROM. Is it better to switch to another protocol to achieve such good performance latency? if so, what open source available solution can have interesting perf. num, wishbone / AHB?
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Hey Xilinx users, let me have it...
You can also look at some of my code, which is all MIT licensed: https://github.com/alexforencich/verilog-axi
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BRAM to AXI Stream in Xilinx Devices
AXI DMA, or the datamover core that the AXI DMA core uses internally, depending on your use case. I also have an open source AXI DMA module that's comparable to the Xilinx datamover core here: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axi_dma.v
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Converting an FPGA design to ASIC
Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
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Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion
I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.
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Assigning values to Verilog parameters from Cocotb?
Thanks for the reply! I ran a particular testbench from your repository but when I placed print statements(print(tb.dut.S_DATA_WIDTH.value) in each test (run_test_write,run_test_read) , I found that it prints out the default parameter value (32) every time.
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Can someone please explain to me the basic parts of a Cocotb testbench?
Here's one of my cocotb testbenches for reference: https://github.com/alexforencich/verilog-axi/blob/master/tb/axi_adapter/test_axi_adapter.py .
What are some alternatives?
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
wb2axip - Bus bridges and other odds and ends
openarty - An Open Source configuration of the Arty platform
verilog-axis - Verilog AXI stream components for FPGA implementation
riscv - RISC-V CPU Core (RV32IM)
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
autofpga - A utility for Composing FPGA designs from Peripherals
FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.
axidmacheck - AXI DMA Check: A utility to measure DMA speeds in simulation
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing
verilog-axi - Verilog AXI components for FPGA implementation