verilog-wishbone
Verilog wishbone components (by alexforencich)
WARP_Core
Wilson AXI RISCV Processor Core (by AEW2015)
Our great sponsors
| verilog-wishbone | WARP_Core | |
|---|---|---|
| 1 | 2 | |
| 98 | 7 | |
| - | - | |
| 0.0 | 0.0 | |
| 4 months ago | almost 4 years ago | |
| Python | VHDL | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog-wishbone
Posts with mentions or reviews of verilog-wishbone.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
WARP_Core
Posts with mentions or reviews of WARP_Core.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing verilog-wishbone and WARP_Core you can also consider the following projects:
litex - Build your hardware, easily!
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
SpinalHDL - Scala based HDL
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
fiate - Fault Injection Automatic Test Equipment
corundum - Open source FPGA-based NIC and platform for in-network compute
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
verilog-wishbone vs litex
WARP_Core vs soft_riscv
verilog-wishbone vs verilog-ethernet
WARP_Core vs verilog-ethernet
verilog-wishbone vs soft_riscv
WARP_Core vs SBusFPGA
verilog-wishbone vs SpinalHDL
WARP_Core vs SpinalHDL
verilog-wishbone vs BYU_PYNQ_PR_Video_Pipeline
WARP_Core vs fiate
verilog-wishbone vs corundum
WARP_Core vs neorv32