riscv VS zipcpu

Compare riscv vs zipcpu and see what are their differences.

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riscv zipcpu
1 13
694 973
- -
0.6 0.8
over 1 year ago about 1 month ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.


Posts with mentions or reviews of zipcpu. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-10-20.
  • Xilinx FIFO generator for skid buffer?
    2 projects | reddit.com/r/FPGA | 20 Oct 2022
    For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
  • OS AXI4 Crossbar with good performance
    4 projects | reddit.com/r/FPGA | 7 Mar 2022
    If you are looking for an AXI4 cache implementation, the ZipCPU currently supports two (I+D) that you might be able to gain some insights from. There's the AXI instruction cache implementation, and an AXI4 data cache implementation. They are both one way caches. Both were featured in an article on performance measurement last year. The data cache implementation doesn't support exclusive access yet--that's still on my to-do list. You can find these caches demonstrated in my AXI DMA check repo, if you'd like to try them out.
  • What modules/hardware would you like to see?
    3 projects | reddit.com/r/FPGA | 14 May 2021
    I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
  • [Help] CPU: Changing from BRAM to real program flash
    5 projects | reddit.com/r/FPGA | 15 Mar 2021
    axilfetch: A basic AXI(lite) fetch unit. This fetch unit fetches instructions into a buffer that can then be fed to the CPU. For the cheapest fetch, set the buffer size FETCH_LIMIT=1. For an AXI version of the ZipCPU's earlier pipelined fetch, set FETCH_LIMIT=2. Higher amounts are also possible, but may not be advantageous.
    5 projects | reddit.com/r/FPGA | 15 Mar 2021
    In some of my early CPU tests, one of my earlier instruction fetches would just keep reading up to 16 instructions ahead of time. I thought this was great until I started examining the resulting performance. The first problem was that it wouldn't release the bus for either a data load or store, and the next problem was that the request was so long the result was often irrelevant by the time it arrived since the CPU had already branched away from the addresses it was fetching.
  • Can someone help me fix my simulation workflow?
    2 projects | reddit.com/r/FPGA | 28 Feb 2021
    That solution isn't all that satisfying to me, so ... I'm trying to do better. My next attempt is going to be 1) using the ZipCPU instead of the ARM (at least for simulation, and certainly instead of a BFM), 2) using AXI instead of Wishbone (Yes, the ZipCPU can now speak either Wishbone or (mostly) AXI), using my own AXI infrastructure (to get rid of the bridges), and using AutoFPGA to compose the design together and handle addressing requirements (instead of Qsys).
  • Soft CPUs - how to debug and test in a sane way?
    4 projects | reddit.com/r/FPGA | 27 Dec 2020
    The ZipCPU is also configurable. It can be built with or without the compressed instruction set. It can be built with or without the multiplier, the divider, or even with or without pipelining. Some configurations have two data buses--one for a nearby set of peripherals, while other configurations do not. Testing the various configurations of the CPU is something I'm not (currently) doing very well. Lord willing, the next version will fix this problem.
    4 projects | reddit.com/r/FPGA | 27 Dec 2020
    When I first built the ZipCPU, I wrote an assembly program to test every CPU instruction. If all tests passed, the CPU would halt and the simulator would detect that as a success. If any test failed, the CPU would go into a busy wait and the simulator would detect that as a failure. One CPU register held within it the number of the current test. I then ran this software on the CPU both normally, and through a single-stepping debug interface. That way I had strong confidence that, once I placed it onto the FPGA, I'd be at least able to use the debugging interface to step the CPU and see the register contents along the way. You can read about what this is like here.
    4 projects | reddit.com/r/FPGA | 27 Dec 2020
    Yes, the ZipCPU is modular. It consists of several components: a pre-fetch (of which there are several to choose from), an instruction decoder, an ALU, a divide unit, a multiply unit, and a memory unit (of which there are multiple to choose from again). Each unit has its own unit tests (proofs--not simulations).

What are some alternatives?

When comparing riscv and zipcpu you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

openarty - An Open Source configuration of the Arty platform

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

wb2axip - Bus bridges and other odds and ends

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.

interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!


uhd - The USRP™ Hardware Driver Repository