riscv vs openlane

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)

#risc-v #Cpu #Verilog #Fpga #Verilator #Rv32im #Rv32i #riscv-linux #pipeline-processor #Asic #Verification

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)

#Asic #130nm #Magic #netgen #yosys #openroad #skywater #openram #vlsi #system-on-chip #soc-design #rtl2gds #Foundry #Rtl #Verilog #klayout #caravel

Source Code

openlane.readthedocs.io

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riscv		openlane
	Project
1	Mentions	11
694	Stars	826
-	Growth	2.5%
0.6	Activity	8.7
over 1 year ago	Latest Commit	1 day ago
Verilog	Language	Verilog
BSD 3-clause "New" or "Revised" License	License	Apache License 2.0

The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.

openlane

Posts with mentions or reviews of openlane. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-12-14.

VLSI Tools
6 projects | reddit.com/r/chipdesign | 14 Dec 2022

OpenLane
Compiling Code into Silicon
10 projects | news.ycombinator.com | 7 Dec 2021
Kickstarting IC design
2 projects | reddit.com/r/chipdesign | 3 Dec 2021

And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
How are modern processors and their architecture designed?
4 projects | reddit.com/r/ECE | 28 Sep 2021

For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
Project Ideas for Uni
2 projects | reddit.com/r/FPGA | 23 Aug 2021

Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.