riscv VS openlane

Compare riscv vs openlane and see what are their differences.

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
Source Code
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openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)
Asic 130nm Magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds Foundry Rtl Verilog klayout caravel
Source Code
openlane.readthedocs.io
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riscv openlane
2 12
1,040 1,168
- 4.3%
1.8 8.6
over 2 years ago 11 days ago
Verilog Python
BSD 3-clause "New" or "Revised" License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

openlane

Posts with mentions or reviews of openlane. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-15.
  • [D][P] Represent Analog Circuits as Graphs
    3 projects | /r/MachineLearning | 15 Apr 2023
    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
  • how small team survive from cadence cost
    1 project | /r/chipdesign | 15 Jan 2023
    There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
  • VLSI Tools
    6 projects | /r/chipdesign | 14 Dec 2022
    OpenLane
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
  • Kickstarting IC design
    2 projects | /r/chipdesign | 3 Dec 2021
    And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
  • How are modern processors and their architecture designed?
    4 projects | /r/ECE | 28 Sep 2021
    For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
  • Project Ideas for Uni
    2 projects | /r/FPGA | 23 Aug 2021
    Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
  • ASIC design post layout for padding.
    1 project | /r/chipdesign | 15 Aug 2021
    I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
  • Resources for a physical design engineer
    1 project | /r/chipdesign | 20 Jul 2021
    Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
  • Intro into chip design
    1 project | /r/chipdesign | 7 May 2021
    https://github.com/efabless/openlane The README is very helpful

What are some alternatives?

When comparing riscv and openlane you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

zipcpu - A small, light weight, RISC CPU soft core

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

rocket-chip - Rocket Chip Generator

uhd - The USRP™ Hardware Driver Repository

NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

opentitan - OpenTitan: Open source silicon root of trust

riscv vs biriscv openlane vs skywater-pdk riscv vs darkriscv openlane vs picorv32 riscv vs zipcpu openlane vs freepdk-45nm riscv vs Toast-RV32i openlane vs rocket-chip riscv vs uhd openlane vs NTHU-ICLAB riscv vs livehd openlane vs opentitan