riscv VS airisc_core_complex

Compare riscv vs airisc_core_complex and see what are their differences.

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
Source Code
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airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
risc-v Riscv Fpga Verilog Embedded Systems AI Asic smart-sensors asil functional-safety Safety Security
Source Code
airisc.de
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riscv airisc_core_complex
2 1
1,040 70
- -
1.8 4.8
over 2 years ago 6 months ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

airisc_core_complex

Posts with mentions or reviews of airisc_core_complex. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-10.

What are some alternatives?

When comparing riscv and airisc_core_complex you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

Hazard3 - 3-stage RV32IMACZb* processor with debug

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zipcpu - A small, light weight, RISC CPU soft core

friscv - RISCV CPU implementation in SystemVerilog

uhd - The USRP™ Hardware Driver Repository

riscv-isa-manual - RISC-V Instruction Set Manual

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

serv - SERV - The SErial RISC-V CPU

riscv vs biriscv airisc_core_complex vs Hazard3 riscv vs openlane airisc_core_complex vs biriscv riscv vs darkriscv airisc_core_complex vs darkriscv riscv vs zipcpu airisc_core_complex vs friscv riscv vs uhd airisc_core_complex vs riscv-isa-manual riscv vs Toast-RV32i airisc_core_complex vs serv