riscv VS airisc_core_complex

Compare riscv vs airisc_core_complex and see what are their differences.

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
#risc-v #Cpu #Verilog #Fpga #Verilator #Rv32im #Rv32i #riscv-linux #pipeline-processor #Asic #Verification
Source Code

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
#risc-v #Riscv #Fpga #Verilog
Source Code
airisc.de
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riscv airisc_core_complex
1 1
742 37
- -
1.0 10.0
over 1 year ago 7 days ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.

airisc_core_complex

Posts with mentions or reviews of airisc_core_complex. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-10.

What are some alternatives?

When comparing riscv and airisc_core_complex you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

zipcpu - A small, light weight, RISC CPU soft core

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

ice40_power - Power analysis of the ICE40UP5K-SG48 devices

uhd - The USRP™ Hardware Driver Repository

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA

riscv vs biriscv
riscv vs openlane
riscv vs zipcpu
riscv vs darkriscv
riscv vs Toast-RV32i
riscv vs ice40_power
riscv vs uhd
riscv vs riscv-cores-list
riscv vs cpu11
riscv vs livehd
riscv vs psram-tang-nano-9k
airisc_core_complex vs darkriscv