lion
wit
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| lion | wit | |
|---|---|---|
| 10 | 5 | |
| 242 | 952 | |
| 0.8% | 1.8% | |
| 4.3 | 5.3 | |
| about 2 months ago | 5 months ago | |
| Haskell | ||
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
lion
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A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
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C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
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Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
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Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
- Lion: A formally verified, 5-stage pipeline RISC-V core
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Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
Where Lions Roam: RISC-V on the VELDT
wit
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Hacker News top posts: Mar 4, 2021
Wit: Wikipedia-Based Image Text Dataset\ (0 comments)
What are some alternatives?
prometheus-cpp - Prometheus Client Library for Modern C++
riscv-formal - RISC-V Formal Verification Framework
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
atomic-story - Understanding how atomics and memory ordering work
witokit - A Python toolkit to generate a tokenized dump of Wikipedia for NLP
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
libcxx - Project moved to: https://github.com/llvm/llvm-project
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
iele-semantics - Semantics of Virtual Machine for IELE prototype blockchain
VELDT-getting-started - Where Lions Roam: Haskell & Hardware on VELDT
WhereIsAI - AI company, product, and tool collection.
solana - Web-Scale Blockchain for fast, secure, scalable, decentralized apps and marketplaces.