lion
VexRiscv
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lion | VexRiscv | |
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10 | 21 | |
242 | 2,244 | |
0.8% | 3.0% | |
4.3 | 7.6 | |
about 2 months ago | 14 days ago | |
Haskell | Assembly | |
BSD 3-clause "New" or "Revised" License | MIT License |
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lion
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A year of RISC-V adventures: embracing chaos in your software journey [video]
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
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C++ Concurrency Model on x86 for Dummies
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
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Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
- Lion is a formally verified, 5-stage pipeline RISC-V core
- Lion: A formally verified, 5-stage pipeline RISC-V core
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Hacker News top posts: Mar 4, 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
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Where Lions Roam: RISC-V on the VELDT
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.
VexRiscv
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
- RISC-V with AXI Peripheral
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Intel discontinues Nios II IP
I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
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Which FPGA for getting into RISC-V?
Something like https://github.com/SpinalHDL/VexRiscv will take far fewer
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Faster CRC32-C on x86
A CPU built around the Gentoo philosophy would look like https://github.com/SpinalHDL/VexRiscv ;). Don't want an MMU? Fine. Need a larger RAM interface? You got it. Barrel ALU for DSP? Sure.
Interpreted languages work by consolidating all of the optimization effort in the interpreter. This is similar to how CPUs work now, instead of extremely specific optimizations that are hard to create distributed among all code we use very general optimizations that push the limits of mathematics that is centralized in a CPU.
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Itanium had a lot of contemporary issues that made it not work. I would certainly blame Intel's business practices and reputation for a large part of it. There are likely niches for such processors. The VLIW is useful for DSP or graphics. Indeed, the only extant VLIW (that I know of) processor is the Russian Elbrus. I think the VLIW is only included to let them reuse a lot of the core logic of the CPU to drive a DSP engine, useful for radar and scientific simulation, though the sci sim would probably use commercial hardware which would be faster.
It works on GPUs because they're doing DSP, basically. We could have weirder topologies for GPUs however, like a massive string of ALUs driven off an embedded core, so you try to kachunk all your data in a single clock domain after configuring the ALU string.
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Looking for a suitable open-source RISC-V for an embedded project
4) https://github.com/SpinalHDL/VexRiscv
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What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.
- Looking for help with RISC-V softcore and VHDL
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Thermal sensor mlx90640 with Nexys 3 fpga
I'd recommend giving vexriscv a look. It'll handily fit on your FPGA, leaving plants of room for I2C, VGA output, and whatever multiplication you end up wanting to do. It's very easy to get set up, and their example "briey" SOC even has VGA output already, but not hardware I2C (though you could easily bitbang it with the core). Adding in I2C via a "plugin" should be trivial.
What are some alternatives?
prometheus-cpp - Prometheus Client Library for Modern C++
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-formal - RISC-V Formal Verification Framework
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
RISCV-FiveStage - Marginally better than redstone
atomic-story - Understanding how atomics and memory ordering work
wb2axip - Bus bridges and other odds and ends
libcxx - Project moved to: https://github.com/llvm/llvm-project
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
wit - WIT (Wikipedia-based Image Text) Dataset is a large multimodal multilingual dataset comprising 37M+ image-text sets with 11M+ unique images across 100+ languages.
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces