soft_riscv
Soft-core RISCV processor for RISCV 2018 competition (by AEW2015)
verilog-wishbone
Verilog wishbone components (by alexforencich)
Our great sponsors
| soft_riscv | verilog-wishbone | |
|---|---|---|
| 1 | 1 | |
| 4 | 98 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | 3 months ago | |
| C | Python | |
| - | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
soft_riscv
Posts with mentions or reviews of soft_riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
verilog-wishbone
Posts with mentions or reviews of verilog-wishbone.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
What are some alternatives?
When comparing soft_riscv and verilog-wishbone you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
litex - Build your hardware, easily!
corundum - Open source FPGA-based NIC and platform for in-network compute
WARP_Core - Wilson AXI RISCV Processor Core
SpinalHDL - Scala based HDL
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
soft_riscv vs verilog-ethernet
verilog-wishbone vs litex
soft_riscv vs corundum
verilog-wishbone vs verilog-ethernet
soft_riscv vs WARP_Core
verilog-wishbone vs SpinalHDL
soft_riscv vs satcat5
verilog-wishbone vs BYU_PYNQ_PR_Video_Pipeline
soft_riscv vs litex
verilog-wishbone vs corundum
verilog-wishbone vs SBusFPGA
verilog-wishbone vs satcat5