soft_riscv
WARP_Core
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soft_riscv | WARP_Core | |
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1 | 2 | |
4 | 7 | |
- | - | |
0.0 | 0.0 | |
over 2 years ago | almost 4 years ago | |
C | VHDL | |
- | - |
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soft_riscv
WARP_Core
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Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
verilog-wishbone - Verilog wishbone components
verilog-ethernet - Verilog Ethernet components for FPGA implementation
corundum - Open source FPGA-based NIC and platform for in-network compute
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
BYU_PYNQ_PR_Video_Pipeline_Hardware - BYU Pynq PR Video Pipeline Hardware
litex - Build your hardware, easily!
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
fiate - Fault Injection Automatic Test Equipment