soft_riscv
Soft-core RISCV processor for RISCV 2018 competition (by AEW2015)
BYU_PYNQ_PR_Video_Pipeline
The Demo that was presented at FCCM. (by byuccl)
Our great sponsors
| soft_riscv | BYU_PYNQ_PR_Video_Pipeline | |
|---|---|---|
| 1 | 2 | |
| 4 | 14 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | over 5 years ago | |
| C | Jupyter Notebook | |
| - | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
soft_riscv
Posts with mentions or reviews of soft_riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
BYU_PYNQ_PR_Video_Pipeline
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing soft_riscv and BYU_PYNQ_PR_Video_Pipeline you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
verilog-wishbone - Verilog wishbone components
SpinalHDL - Scala based HDL
corundum - Open source FPGA-based NIC and platform for in-network compute
WARP_Core - Wilson AXI RISCV Processor Core
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
soft_riscv vs verilog-ethernet
BYU_PYNQ_PR_Video_Pipeline vs verilog-ethernet
soft_riscv vs verilog-wishbone
BYU_PYNQ_PR_Video_Pipeline vs SpinalHDL
soft_riscv vs corundum
BYU_PYNQ_PR_Video_Pipeline vs corundum
soft_riscv vs WARP_Core
BYU_PYNQ_PR_Video_Pipeline vs verilog-wishbone
soft_riscv vs satcat5
BYU_PYNQ_PR_Video_Pipeline vs satcat5