rust-lsp-proxy
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rust-lsp-proxy
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Tracking mentions began in Dec 2020.
svls
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How to configure vim like an IDE
svls
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
I can attest first-hand to the "headache" that comes from semi company simulation environments. Not only are they horribly outdated (in Perl/Tcl), but they're different at every company you work at. There's no gold standard because the standard that these EDA companies ought to be making doesn't exist.
There needs to be an open initiative between semi companies to create a standard simulation environment -- with compilers, unit-test frameworks, and all sorts of simulation (gate-level, analog/mixed signal, emulation, etc). Hell, just give me a free IDE plugin for SystemVerilog that actually works.
This lack of a standard seems to me like the critical path in hardware design. I'm trying to support projects to fix this like SVLS (A language server for SystemVerilog: https://github.com/dalance/svls) but these are all hard problems to solve. This industry is relatively niche and doesn't seem to have many engineers interested in FOSS.
What are some alternatives?
ws-tool - High perform & easy to use websocket client/server
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
sozu - Sōzu HTTP reverse proxy, configurable at runtime, fast and safe, built in Rust. It is awesome!
veridian - A SystemVerilog Language Server
texlab - An implementation of the Language Server Protocol for LaTeX
lucia - A flexible client API framework as well as a set of API collections
Verilog.jl - Verilog for Julia
yerpc - An ergonomic JSON-RPC server library in Rust with autocreated TypeScript client and OpenRPC specification
circt - Circuit IR Compilers and Tools
RecursiveFactorization.jl
Modia.jl - Modeling and simulation of multidomain engineering systems