riscv_vhdl
Ripes
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| riscv_vhdl | Ripes | |
|---|---|---|
| 2 | 18 | |
| 578 | 2,355 | |
| - | - | |
| 8.8 | 7.2 | |
| 4 months ago | 20 days ago | |
| Verilog | C++ | |
| Apache License 2.0 | MIT License |
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riscv_vhdl
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Wouldn't it be crazy if amd or intel turned around and started making RISK-V based processors to compete with arm?
There is code that describes the processor, the VHDL is also open source. You can get the some similar implementations for older ARM implementations but you may have to pay to use them commercially.
- What is a list of all softcores that were designed purely using VHDL?
Ripes
- Web GUI for the Ripes RISC-V simulator
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C++ or Rust after having learnt C ?
Are you talking about projects such as this? https://github.com/mortbopet/Ripes
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Hardware/software to run RISC-V ASM?
If you want to see more what is going on under the hood of a RISC-V CPU you could use the graphical simulator Ripes: https://github.com/mortbopet/Ripes
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Open-source RISC-V simulator suggestions?
https://github.com/mortbopet/Ripes is in c++
- Ripes: Visual computer architecture simulator, assembly code editor for RISC-V
- Emulator (not qemu) for learning risc-v without Just In Time execution?
- Compiling RV32I assembly without C in Freedom?
What are some alternatives?
verilator - Verilator open-source SystemVerilog simulator and lint system
rars - RARS -- RISC-V Assembler and Runtime Simulator
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
jupiter - RISC-V Assembler and Runtime Simulator
microwatt - A tiny Open POWER ISA softcore written in VHDL 2008
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
edb-debugger - edb is a cross-platform AArch32/x86/x86-64 debugger.
nightmare
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
awesome-hdl - Hardware Description Languages
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Kite - Kite: Architecture Simulator for RISC-V Instruction Set