riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel (by ucb-bar)
RISCV-FiveStage
Marginally better than redstone (by PeterAaser)
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| riscv-mini | RISCV-FiveStage | |
|---|---|---|
| 1 | 4 | |
| 491 | 89 | |
| 4.3% | - | |
| 3.8 | 0.0 | |
| about 1 month ago | over 3 years ago | |
| Scala | Scala | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-mini
Posts with mentions or reviews of riscv-mini.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-15.
RISCV-FiveStage
Posts with mentions or reviews of RISCV-FiveStage.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-15.
- Tips on building a RISC-V processor on FPGA
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Planning to develop a CPU on an FPGA. How can I program it?
I can recommend the coursework that I made for my university. It uses chisel (similar to verilog but less finickity and annoying) to create a five stage RISC-V 32I capable processors that can run small bare metal programs. The intro: https://github.com/PeterAaser/tdt4255-chisel-intro The 5-stage: https://github.com/PeterAaser/RISCV-FiveStage
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Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer
It's coursework that takes you from knowing nothing about hardware design to designing your own RISC-V In-Order Five stage architecture. As far as I know a few students have actually done the work to run this on an FPGA, but for the most part you will have the luxury of an emulator, giving you things like stack traces compared to the model execution for all the test programs etc.
https://github.com/PeterAaser/RISCV-FiveStage
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Want to get started.What to buy?
If you want to do something big but simulated you can try to do this coursework https://github.com/PeterAaser/RISCV-FiveStage I made for my university, teaching CPU design. It's in chisel though, which is different from verilog. Be sure to look at the intro first.
What are some alternatives?
When comparing riscv-mini and RISCV-FiveStage you can also consider the following projects:
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-tests
cortex-m0-soft-microcontroller - Soft-microcontroller implementation of an ARM Cortex-M0
chisel - Chisel: A Modern Hardware Design Language
litex - Build your hardware, easily!