riscv-boom
rocket-chip
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riscv-boom | rocket-chip | |
---|---|---|
12 | 12 | |
1,584 | 2,990 | |
2.1% | 1.7% | |
7.2 | 8.3 | |
about 1 month ago | 5 days ago | |
Scala | Scala | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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RSD is a open source high performance RISC-V Processor
The SonicBOOM from Berkeley is on paper superior as it supports the 64-bit ISA.
rocket-chip
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
- Can anyone explain simply how OpenSource the RISC-V actually is?
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Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
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How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
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Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
You should start tracing through the code to see what that requirement means. Grep through the github repo for things like "rowBits", which brings up this issue (https://github.com/chipsalliance/rocket-chip/issues/1352) which may be relevant to your interests.
What are some alternatives?
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
openc910 - OpenXuantie - OpenC910 Core
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
XiangShan - Open-source high-performance RISC-V processor
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
Cores-VeeR-EL2 - VeeR EL2 Core
Cores-VeeR-EH1 - VeeR EH1 core
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K