peakperf
XiangShan
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peakperf | XiangShan | |
---|---|---|
2 | 32 | |
56 | 4,260 | |
- | 1.9% | |
4.4 | 9.3 | |
about 1 month ago | 6 days ago | |
C++ | Scala | |
GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
peakperf
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lscpu + neofetch = cpufetch
Dr-Noob here. Created an account just to comment on this post. I appreciate all of your comments.
For the ones who think that cpufetch uses lscpu (especially the one who wrote the title of this post), please see https://www.reddit.com/r/linux/comments/milnza/cpufetch_simp...
About the peak performance, nezirus, the purpose is to have a quick look of how powerful a CPU is supposed to be. Peak performance does not measure the real performance of a CPU but it is a rough estimate of it. The peak performance is one of the distinguishing marks of cpufetch and is one of my favorite fields of cpufetch. Concerning the fight between Gold 6238 and EPYC 7702P, is not the other way around. If you are able to use the full power of the CPU, Gold is much more powerful. However, in a real program, this is not always true. For more information about the peak performance, see https://github.com/Dr-Noob/peakperf. There you will understand how peak performance is calculated and how it works.
Thank you very much for your "text screenshots", I really like to see my program on all this variety of hardware!
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cpufetch - Simplistic yet fancy CPU architecture fetching tool (supports x86_64 and ARM)
If you are interested, you can find more information in another project of mine, peakperf (https://github.com/Dr-Noob/peakperf).
XiangShan
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Loongson 3A6000: A Star Among Chinese CPUs
Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.
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MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).
You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...
Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.
> Perhaps they will provide compiler patches if required.
I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...
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Ask HN: Are there any open source dual-issue RISC-V processor
This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan
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How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
Maybe implement a big feature for a open source design? like vroom or xiangshan.
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
- Open-source high-performance RISC-V processor
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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
Here’s a good example of one: https://github.com/OpenXiangShan/XiangShan
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
There are already open source designs that are reportedly close to older ARM smartphone design in term of performance (c910 and xiangshang).
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RISC-V Pushes into the Mainstream
> Because at this point they have more to gain than by keeping them proprietary. RISC-V is not yet overall competitive with ARM. So it's not like these RISC-V cores could be commercialized that successfully. Keeping them open probably makes further development faster.
This open source core is about equivalent to a Cortex-X1. https://github.com/OpenXiangShan/XiangShan
- VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
openc910 - OpenXuantie - OpenC910 Core
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
chisel - Chisel: A Modern Hardware Design Language
oneMKL - oneAPI Math Kernel Library (oneMKL) Interfaces
cpufetch - Simple yet fancy CPU architecture fetching tool
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
png2ascii - Lightning fast ASCII image generator
kth - High performance Bitcoin development platform
vroom - VRoom! RISC-V CPU
block-inclusivecache-sifive