panologic
panologic-g2
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| panologic | panologic-g2 | |
|---|---|---|
| 3 | 5 | |
| 68 | 130 | |
| - | - | |
| 3.7 | 0.0 | |
| 18 days ago | almost 3 years ago | |
| Verilog | Verilog | |
| - | Apache License 2.0 |
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panologic
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Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
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Cheap (or Free FPGAs)
Here is my GitHub repo: https://github.com/tomverbeure/panologic
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Risc-v with minimum number of gates
That's the approach I use in all my hobby projects. Do I really need that I2C controller? Of course not, I just bitbang it on a VexRiscv CPU...
panologic-g2
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Chisel: A Modern Hardware Design Language
I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset.
Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing.
Here's an example of an APB bridge with clock domain crossing: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal....
The module takes the 2 domains as object parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
Here's the code that lives in the APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
This is the destination clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
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Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
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Making my first game on FPGA
If you are okay with using a Spartan 6 device and ISE WebPACK, a Panologic G2 has 100k LUT6s, extra RAM and flash, Ethernet, USB, and two DVI/HDMI outputs, for under $50. Here's a github page, about developing for one.
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Looking for someone who has a good amount of FPGA's that are suitable for cracking bcrypt
If you send me a bitstream, I can try running it, but it will need to provide a way to communicate with the outside world, e.g. over the USB or Ethernet ports. There are hardware details here: https://github.com/tomverbeure/panologic-g2
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JTAG Programmer for Pano Logic G2?
I picked up a Pano Logic G2 for cheap and need to get a JTAG programmer for it. I'd like to use the Altera toolset. Is there an inexpensive JTAG programmer that I can use for this? I'm not at all familiar with JTAG and having a hard time figuring out what I'd miss out on by going with an off brand programmer.
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
pin-uart - FPGA board-level debugging and reverse-engineering tool
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.