open-register-design-tool
biriscv
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open-register-design-tool | biriscv | |
---|---|---|
2 | 6 | |
181 | 749 | |
2.2% | - | |
5.3 | 0.0 | |
9 months ago | over 2 years ago | |
Verilog | Verilog | |
Apache License 2.0 | Apache License 2.0 |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
biriscv
What are some alternatives?
rggen - Code generation tool for control and status registers
riscv - RISC-V CPU Core (RV32IM)
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
zipcpu - A small, light weight, RISC CPU soft core
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
vgasim - A Video display simulator
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
wbicapetwo - Wishbone to ICAPE interface conversion