neorv32
riscv-asm-manual
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| neorv32 | riscv-asm-manual | |
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| 77 | 8 | |
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neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
riscv-asm-manual
- RISC-V Assembler: Arithmetic
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RISC-V assembler input file format
This document has most of the explanations about the input format: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md. There are some small missing bits but all the directives like .text are there.
- If you were to start your coding journey from zero, what would be your plan?
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Question about RISC-V development
The is a C and C++ toolchain available https://github.com/riscv-collab/riscv-gnu-toolchain If you feeling brave, https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
- Is there any documentation relates to the riscv-gnu-toolchain ?
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Examples of RISC-V Assembly Programs
> Note: "jalr zero, 1b" can also be written as "j 1b", "jalr zero, 0(ra)" can be written as "ret"
`j` and `ret` are so-called "pseudo instructions" [1], not compressed instructions.
Pseudo instructions are just shortcuts used in assembly language to pretend that some common operations really "exist" with the need to type (or display) the real, more complex instructions. `nop` is a common pseudo instruction. RISC-V has `nop` instructions, but, instead, the "do nothing instruction" is canonically encoded as `addi x0, x0, 0`.
The compressed instruction set (a.k.a "extension C") is a subset of the full [2] instruction set, in which a restricted combinations of operands are possible. The assembly (human readable) code of the compressed instruction set looks similar to that of the full instruction set (including pseudo instructions), but they are encoded as completely different binary sequences.
[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-...
[2] https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf#...
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RISCV Assembly and absolute addressing ?
This should be helpful https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md
- Absolute beginner to RISC-V, where do I start?
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
glibc - GNU Libc
picoMIPS - picoMIPS processor doing affine transformation
riscv-isa-manual - RISC-V Instruction Set Manual
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
arduino-6502ctl - Arduino 6502 Controller
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!