neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
Our great sponsors
| neorv32 | fusesoc | |
|---|---|---|
| 77 | 12 | |
| 1,415 | 1,115 | |
| - | - | |
| 9.9 | 7.6 | |
| 8 days ago | 14 days ago | |
| C | Python | |
| BSD 3-clause "New" or "Revised" License | BSD 2-clause "Simplified" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32
Posts with mentions or reviews of neorv32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
-
Recommendations for RISC-V on FPGA
How about NEORV32?
-
SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
-
RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
-
Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
-
fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
-
Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
-
CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
-
Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
-
Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
-
Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
-
Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
-
What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
What are some alternatives?
When comparing neorv32 and fusesoc you can also consider the following projects:
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
litex - Build your hardware, easily!
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
edalize - An abstraction library for interfacing EDA tools
picoMIPS - picoMIPS processor doing affine transformation
opentitan - OpenTitan: Open source silicon root of trust
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
rocket-chip - Rocket Chip Generator