logisim-evolution
iverilog
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logisim-evolution | iverilog | |
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25 | 11 | |
4,307 | 2,627 | |
4.3% | - | |
9.4 | 9.6 | |
1 day ago | 4 days ago | |
Java | C++ | |
GNU General Public License v3.0 only | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
logisim-evolution
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Problem with installation
I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.
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Creating a package that requires Java 16
I am trying to define an xbps-src template for logisim-evolution, a Java app that requires Java 16. I am using depends="virtual?java-runtime" and, as expected by reading etc/defaults.virtual, OpenJDK 8 is used. Creating a etc/virtual file is ignored in .gitignore, so I guess it is made to be used with local packages. Using depends="virtual?java-runtime-17.0.5+7_1" works, as OpenJDK 17 provides that exact version of java-runtime. If it were updated, this package would break, because if I input a lower version, it will fail. I've tried using syntax like > and >=, but then I get the following error:
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A circuit simulator that doesn't look like it was made in 2003
Logism evolution works great and is quite modern.
https://github.com/logisim-evolution/logisim-evolution
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Hi there, I got an assigment that consists of moving a stepper motor (4 phases) using only a 74LS76N and a 74LS86N but when I tried to use the schematic, it didn't work, any help would be extremely helpful (more info in comments)
According to Logisim it creates the correct sequence for full stepping on a bipolar configuration. Falstad's Circuit simulator is another one you might try.
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Help needed to find FOSS tools to create graphical logic circuits and convert them to VHDL in class.
Did you check logisim-evolution? It is an active fork of logisim maintained by several lecturers at the Bern University of Applied Sciences.
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Ben Eater's 8-Bit CPU in Logisim, Plus More!
Here is the link for Logisim Evolution: https://github.com/logisim-evolution/logisim-evolution
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Crumb Circuit Simulator
In school, I worked on an introductory CS/EE class many, many moons ago, and I believed we used something like "logisim", which by then was pretty awesome - you could build simple things like adders, combine those with "macros" to bui;d ALUs and then whole simple CPUs.
Since then, the logisim project has discontinued, but it looks like there is a open source successor:
https://github.com/logisim-evolution/logisim-evolution
Have not tried it, but it looks promising, provided you don't want to do too complicated things (not sure if you could really model complex CPUs like a pentium with it). Also, it's pretty digital only, so I wouldn't expect Mac-Spice-like analog circuit simulation.
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I was making adder circuits in games 8 years ago in an attempt to build a computer. I finally worked my way up and built a working computer!
though i'd heavily recommend first building the circuit in a logic simulator like Logisim, or Digital before trying to build it in a game for an FPGA. (Digital even allows you to export circuits as Verilog/VHDL, and as a certified lazy person, that is very useful)
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Embedded Systems Weekly #112
Logisim-evolution An alternative free and open-source tool to design and simulate digital logic.
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Tang Nano 9K – FPGA SBC with HDMI
See if you are comfortable playing in https://github.com/logisim-evolution/logisim-evolution
iverilog
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Which System Verilog Simulator to use if I need SVA Assertions?
Also, Icarus says that they do not support assertions in their full-generality either:
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Trying to learn and work with FPGAs
The toolchains come with their own simulators, but there are also open source ones you can use. For Verilog you have ICARUS Verilog and Verilator. For VHDL there is GHDL.
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Open-source SystemVerilog simulation support using cocotb
This is not, in general, true. While iverilog may support some SV features, it is far from complete and does not support some very common use cases. For example, interfaces.
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Order of assignments in verilog
However, I find that it's always read-before-write in Icarus Verilog. Is my tool wrong? Is the book wrong? Is this situation actually ambiguous?
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Ben's 8 Bit Computer in an FPGA
I have no intention to run it on real FPGA ever, Icarus Verilog simulator suits me well enough.
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Building the 8-bit computer in software
As the idea was to make it more realistic, I started by making (hopefully accurate representation of) 74-series logic chips in Verilog. Then wired them into higher level modules, and merged those into complete CPU. Runs quite good in Icarus Verilog.
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Where do I start with RISC-V/
I'd suggest starting with simulation using Icarus Verilog or Verilator. And gtkwave to display simulation output.
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100 Languages Speedrun: Episode 28: Verilog
We'll specifically be using Icarus Verilog.
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Transition from soc Design to Design Verification?
In the open-source world, learning UVM isn't practical. There just isn't a simulator that can run it. However, if you use something like PyUVM with CocoTB, along with verilator or Icarus as an RTL simulator you code start writing test benches around some simple verilog components.
- How much to buy these tools? I got this from openfpga website, thanks
What are some alternatives?
Digital - A digital logic designer and circuit simulator.
slang - SystemVerilog compiler and language services
logisim-evolution - Digital logic designer and simulator
veridian - A SystemVerilog Language Server
32-bit-RISC-V-Cpu-Core
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
RISC-V-Computer - An enhanced yet simplified version of the original RISC-V-Computer build with Logisim [Moved to: https://github.com/MazinCE/RVCOM2.0]
pyuvm - The UVM written in Python
ghdl - VHDL 2008/93/87 simulator
8-bit-CPU - Homebrew 8-bit CPU