|2 days ago||about 1 month ago|
|GNU General Public License v3.0 or later||ISC License|
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Tracking mentions began in Dec 2020.
How many LUT for an 8 bit CPU?
2 projects | reddit.com/r/FPGA | 11 Nov 2022
Minimax: a Compressed-First, Microcoded RISC-V CPU
4 projects | reddit.com/r/FPGA | 26 Oct 2022
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
Apple to Move a Part of Its Embedded Cores to RISC-V
4 projects | news.ycombinator.com | 16 Sep 2022
I have created a Reddit community about PicoBlaze soft processor...
2 projects | reddit.com/r/FPGA | 13 Sep 2022
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
3 projects | news.ycombinator.com | 21 Jun 2022
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
looking for 16 bit RISC ISA to implement on cyclon IV FPGA
2 projects | reddit.com/r/FPGA | 25 Feb 2022
SERV has an RV32I ISA. It is really light. I am sure it will fit.
Risc-v with minimum number of gates
3 projects | reddit.com/r/FPGA | 11 Jan 2022
Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
3 projects | reddit.com/r/RISCV | 24 Sep 2021
RISCV sim through Verilator
3 projects | reddit.com/r/FPGA | 29 Aug 2021
I have tested SERV on Verilator. It was working without any problems.
Glacial – microcoded RISC-V core designed for low FPGA resource utilization
3 projects | news.ycombinator.com | 20 Mar 2021
Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv
From time to time, I have been tempted to design a RISC-V implementation out of discrete TTL components. Sure, there are plenty of projects out there to build your own processor from scratch, but most of them aren't LLVM targets!
The 32-bit datapaths and need for so many registers makes it a bit daunting to approach directly. That approach would probably end up similar in scale to a MIPS implementation I once saw done like that. (Can't find the link, but it was about half a dozen A4-sized PCBs).
Retreating to an 8-bit microcoded approach and lifting all the registers and complexity into RAM and software is a very attractive idea. It's not like it would ever be a speed demon, either way.
What are some alternatives?
neorv32 - 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
edalize - An abstraction library for interfacing EDA tools
riscv_verilator_model - RISCV model for Verilator/FPGA targets
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
ContrAlto - This repository contains the source code for Living Computers: Museum+Labs's Xerox Alto emulator, ContrAlto.
hdl - HDL libraries and projects
IronOS - Open Source Soldering Iron firmware for Miniware and Pinecil
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones