livehd
open-register-design-tool
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| livehd | open-register-design-tool | |
|---|---|---|
| 1 | 2 | |
| 197 | 181 | |
| 1.0% | 2.2% | |
| 9.2 | 5.3 | |
| 6 days ago | 9 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
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livehd
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
What are some alternatives?
hdl - HDL libraries and projects
rggen - Code generation tool for control and status registers
riscv - RISC-V CPU Core (RV32IM)
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
biriscv - 32-bit Superscalar RISC-V CPU
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
serv - SERV - The SErial RISC-V CPU
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication