hdl
viv-prj-gen
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| hdl | viv-prj-gen | |
|---|---|---|
| 5 | 8 | |
| 1,374 | 21 | |
| 4.2% | - | |
| 9.0 | 1.9 | |
| about 21 hours ago | 10 months ago | |
| Verilog | CMake | |
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
viv-prj-gen
- CI/CD for FPGA builds
- Vivado 2020.2 IP Repository Suggestion
- Comments and rants about tools, and a crazy idea
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Is it just me/my company or do FPGA tools and workflows suck at common software development practices like collaboration and CI/CD?
I wrote a similar cmake based project https://github.com/TripRichert/viv-prj-gen . It is no longer maintained (I wrote it as a personal project, but don't think I ever got any users for it, and can't contribute to it from work). But, It has got a tutorial https://github.com/TripRichert/viv-prj-gen/blob/master/tutorial/Tutorial.adoc , so you could check it out and see an automated workflow that I think is easy to get started with. This might give you some ideas how things could work.
- How do you manage your Vivado projects in git?
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Industry development process?
here's my script that does something similar https://github.com/TripRichert/viv-prj-gen/blob/master/tcl/gen_xactip.tcl
- What scripting languages are used in your job to help automate the design flow?
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Vivado_NonProjectMode_Example - An Basic Example and outline of the Vivado non Project mode Workflow
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
corundum - Open source FPGA-based NIC and platform for in-network compute
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
ghdl - VHDL 2008/93/87 simulator
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
Documentation - OSVVM Documentation
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.