hdl
HDL libraries and projects (by analogdevicesinc)
cpu11
Revengineered ancient PDP-11 CPUs, originals and clones (by 1801BM1)
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| hdl | cpu11 | |
|---|---|---|
| 5 | 2 | |
| 1,374 | 146 | |
| 4.2% | - | |
| 9.0 | 5.3 | |
| 7 days ago | 5 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl
Posts with mentions or reviews of hdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-01.
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
-
Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
-
Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
cpu11
Posts with mentions or reviews of cpu11.
We have used some of these posts to build our list of alternatives
and similar projects.
- Dec F11 precise replica in Verilog, based on reverse engineering of real dies
-
I finally got a PDP-8i (sort of).
There are quite a few HDL implementations, eg CPU11 and this list.
What are some alternatives?
When comparing hdl and cpu11 you can also consider the following projects:
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
PDP-11 - A collection of PDP-11 related files
serv - SERV - The SErial RISC-V CPU
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
riscv - RISC-V CPU Core (RV32IM)
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
zipcpu - A small, light weight, RISC CPU soft core