hdl
basic-ecp5-pcb
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| hdl | basic-ecp5-pcb | |
|---|---|---|
| 5 | 1 | |
| 1,374 | 85 | |
| 4.2% | - | |
| 9.0 | 0.0 | |
| 7 days ago | almost 3 years ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | Creative Commons Zero v1.0 Universal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
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Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
basic-ecp5-pcb
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Power IC for ECP5
See e.g. https://github.com/mattvenn/basic-ecp5-pcb
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
orangecrab-hardware - ECP5 breakout board in a feather physical format
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
butterstick-hardware - Basic ECP5 based GigE to SYZYGY interface.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
SummerCart64 - SummerCart64 - a fully open source Nintendo 64 flashcart
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
FusionConverter - Design files for the open-hardware NeoGeo MVS to AES converter
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
corundum - Open source FPGA-based NIC and platform for in-network compute
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
clash-pong - Pong in Haskell / Clash, running as software using SDL and as hardware targeting FPGAs