hdl
OpenTimer
Our great sponsors
| hdl | OpenTimer | |
|---|---|---|
| 5 | 1 | |
| 1,374 | 511 | |
| 4.2% | 2.2% | |
| 9.0 | 0.0 | |
| 7 days ago | 11 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl
-
Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
-
Anyone else feeling extremely frustrated with Xilinx?
The reference designs from Analog Devices are all hand coded complex block designs for both Intel and Xilinx: https://github.com/analogdevicesinc/hdl
-
Intel Quartus Version Control?
There’s 100 million ways people skin this cat. Some people guard this like it’s fort know. ADI publishes theirs on GitHub in adi_hdl that supports both vivado and quartus. https://github.com/analogdevicesinc/hdl
-
Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
OpenTimer
-
Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
serv - SERV - The SErial RISC-V CPU
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
zipcpu - A small, light weight, RISC CPU soft core
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
FPGA_SDRAM_Controller - SDRAM controller optimized to a memory bandwidth of 316MB/s
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.