fusesoc_template
icicle
| fusesoc_template | icicle | |
|---|---|---|
| 1 | 1 | |
| 15 | 301 | |
| - | - | |
| 1.8 | 6.0 | |
| over 3 years ago | over 1 year ago | |
| Python | Python | |
| - | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc_template
-
Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
icicle
-
"AMD Extends the UltraScale+ Product Portfolio"
If you just need a system to practice VHDL / Verilog on, the $50 entry point is a bit better. It won't be fast or big, but there's plenty to do and learn on something like that. The ICE40 is large enough to get a RISCV core for example.
What are some alternatives?
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
kianRiscV - RISC-V Linux SoC, marchID: 0x2b
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
edalize - An abstraction library for interfacing EDA tools
PlatformIO - Your Gateway to Embedded Software Development Excellence :alien:
icicle - An OSS CAD Suite Version Manager