fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
viv-prj-gen
tcl scripts used to build or generate vivado projects automatically (by TripRichert)
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| fusesoc | viv-prj-gen | |
|---|---|---|
| 12 | 8 | |
| 1,115 | 21 | |
| - | - | |
| 7.6 | 1.9 | |
| 12 days ago | 10 months ago | |
| Python | CMake | |
| BSD 2-clause "Simplified" License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
viv-prj-gen
Posts with mentions or reviews of viv-prj-gen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-11.
- CI/CD for FPGA builds
- Vivado 2020.2 IP Repository Suggestion
- Comments and rants about tools, and a crazy idea
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Is it just me/my company or do FPGA tools and workflows suck at common software development practices like collaboration and CI/CD?
I wrote a similar cmake based project https://github.com/TripRichert/viv-prj-gen . It is no longer maintained (I wrote it as a personal project, but don't think I ever got any users for it, and can't contribute to it from work). But, It has got a tutorial https://github.com/TripRichert/viv-prj-gen/blob/master/tutorial/Tutorial.adoc , so you could check it out and see an automated workflow that I think is easy to get started with. This might give you some ideas how things could work.
- How do you manage your Vivado projects in git?
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Industry development process?
here's my script that does something similar https://github.com/TripRichert/viv-prj-gen/blob/master/tcl/gen_xactip.tcl
- What scripting languages are used in your job to help automate the design flow?
What are some alternatives?
When comparing fusesoc and viv-prj-gen you can also consider the following projects:
litex - Build your hardware, easily!
Vivado_NonProjectMode_Example - An Basic Example and outline of the Vivado non Project mode Workflow
edalize - An abstraction library for interfacing EDA tools
corundum - Open source FPGA-based NIC and platform for in-network compute
opentitan - OpenTitan: Open source silicon root of trust
ghdl - VHDL 2008/93/87 simulator
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Documentation - OSVVM Documentation
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
rocket-chip - Rocket Chip Generator
hdl - HDL libraries and projects
fusesoc vs litex
viv-prj-gen vs Vivado_NonProjectMode_Example
fusesoc vs edalize
viv-prj-gen vs corundum
fusesoc vs opentitan
viv-prj-gen vs ghdl
fusesoc vs cocotb
viv-prj-gen vs Documentation
fusesoc vs teroshdl-documenter-demo
viv-prj-gen vs OsvvmLibraries
fusesoc vs rocket-chip
viv-prj-gen vs hdl