fusesoc
satcat5
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| fusesoc | satcat5 | |
|---|---|---|
| 12 | 25 | |
| 1,112 | 382 | |
| - | 35.9% | |
| 7.6 | 3.8 | |
| 5 days ago | about 2 months ago | |
| Python | VHDL | |
| BSD 2-clause "Simplified" License | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Are you aware of FuseSoC: https://github.com/olofk/fusesoc? It's a build system for HDL that uses edalize so it can target many different tools.
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
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FPGA development board for beginners programmable w/ floss toolchain
I'd recommend looking at fusesoc to automate flows: https://github.com/olofk/fusesoc
satcat5
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Show HN: SatCat5, the open-source FPGA Ethernet switch
Hi!
I'm one of the engineers working with cubesat hardware and software integration, and I've been following this project since 2023 because I agree that standardizing over Ethernet over (twisted pair, UART, single pair, etc...) will solve a lot of integration pain from all of the DIY protocols that the cubesat/smallsat community uses
Some thoughts:
- You actually have a publicly available ICD at https://github.com/the-aerospace-corporation/satcat5/tree/ma... , please publicize this more in the readme! You're a very rare exception in a world of contact us and sign an NDA first and commercial in confidence ICDs, which is great, and leads me to my next point:
- Compared to HTTP API documentation, space ICDs sucks. One of the ICDs that I have put its protocol documentation as screenshots instead of copy pasteable text. Of course ICDs sucks because you won't know its quality until you buy it... Anyway standardizing on ethernet for transport layer give you all the tooling at 99% of the world's computer use, and it might be a first step in making a OpenAPI / Swagger type tool but for space protocols
- Any plans for 10base-T1S single pair ethernet? Our 6U cubesats barely have enough power to run its payload computers, let alone a FPGA based switch. But in a way a switched star network can be more reliable than a multidrop bus, as you can isolate babbling idiot nodes, and filter out accidental/intentional MAC/IP address spoofing
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
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Looking for a GitHub repo which contains unit tests
Here's a C++ example using Catch.
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Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
Cross-platform support for RMII and RGMII.
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1G Ethernet Using SGMII PHY
SatCat5 includes an open source SGMII MAC using LVDS GPIO on 7-Series FPGAs. Please note since of the platform-specific logic will need some adaptation for Ultrascale+.
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Ethernet on FPGA
Here's an RMII interface core.
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SatCat5 version 2.1 update
The SatCat5 team just posted version 2.1 to GitHub.
- Any recommendations for an RTL "standard library"?
What are some alternatives?
litex - Build your hardware, easily!
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rocket-chip - Rocket Chip Generator
verilog-ethernet - Verilog Ethernet components for FPGA implementation
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SpinalHDL - Scala based HDL
serv - SERV - The SErial RISC-V CPU
hdl - HDL libraries and projects