fusesoc
hdl
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fusesoc | hdl | |
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11 | 5 | |
1,103 | 1,340 | |
- | 3.1% | |
7.6 | 9.0 | |
9 days ago | 7 days ago | |
Python | Verilog | |
BSD 2-clause "Simplified" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Are you aware of FuseSoC: https://github.com/olofk/fusesoc? It's a build system for HDL that uses edalize so it can target many different tools.
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
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FPGA development board for beginners programmable w/ floss toolchain
I'd recommend looking at fusesoc to automate flows: https://github.com/olofk/fusesoc
hdl
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Timing diagram help
Have you thought about using ADs source code and pulling what you need to create a front end to their device?
- Vivado 2020.2 IP Repository Suggestion
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Industry development process?
I haven't used this repo, but something like this https://github.com/analogdevicesinc/hdl/tree/master/library
What are some alternatives?
litex - Build your hardware, easily!
edalize - An abstraction library for interfacing EDA tools
opentitan - OpenTitan: Open source silicon root of trust
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rocket-chip - Rocket Chip Generator
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
serv - SERV - The SErial RISC-V CPU
viv-prj-gen - tcl scripts used to build or generate vivado projects automatically
VHDL_Lib - Library of VHDL components that are useful in larger designs.
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.