fusesoc VS hdl

Compare fusesoc vs hdl and see what are their differences.

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development (by olofk)

hdl

HDL libraries and projects (by analogdevicesinc)
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fusesoc hdl
11 5
1,103 1,340
- 3.1%
7.6 9.0
9 days ago 7 days ago
Python Verilog
BSD 2-clause "Simplified" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

fusesoc

Posts with mentions or reviews of fusesoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.

hdl

Posts with mentions or reviews of hdl. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-01.

What are some alternatives?

When comparing fusesoc and hdl you can also consider the following projects:

litex - Build your hardware, easily!

edalize - An abstraction library for interfacing EDA tools

opentitan - OpenTitan: Open source silicon root of trust

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

rocket-chip - Rocket Chip Generator

vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

serv - SERV - The SErial RISC-V CPU

viv-prj-gen - tcl scripts used to build or generate vivado projects automatically

VHDL_Lib - Library of VHDL components that are useful in larger designs.

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.