fusesoc
edalize
Our great sponsors
fusesoc | edalize | |
---|---|---|
12 | 4 | |
1,112 | 587 | |
- | - | |
7.6 | 7.3 | |
8 days ago | 7 days ago | |
Python | Python | |
BSD 2-clause "Simplified" License | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
-
fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
-
Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
-
CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
-
Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
-
Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
-
Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
-
Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
-
What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
edalize
-
Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
-
Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
-
Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
litex - Build your hardware, easily!
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
opentitan - OpenTitan: Open source silicon root of trust
apio - :seedling: Open source ecosystem for open FPGA boards
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
icestudio - :snowflake: Visual editor for open FPGA boards
rocket-chip - Rocket Chip Generator
rggen - Code generation tool for control and status registers
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
sphinx-vhdl