friscv VS cv32e40p

Compare friscv vs cv32e40p and see what are their differences.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform (by openhwgroup)
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friscv cv32e40p
1 3
14 861
- 2.3%
8.4 9.1
about 2 months ago 3 days ago
Coq SystemVerilog
MIT License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

friscv

Posts with mentions or reviews of friscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

cv32e40p

Posts with mentions or reviews of cv32e40p. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning cv32e40p yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing friscv and cv32e40p you can also consider the following projects:

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

riscv-simple-sv - A simple RISC V core for teaching

Cores-VeeR-EL2 - VeeR EL2 Core

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Cores-VeeR-EH1 - VeeR EH1 core

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.