friscv VS airisc_core_complex

Compare friscv vs airisc_core_complex and see what are their differences.

friscv

RISCV CPU implementation in SystemVerilog (by dpretet)
riscv-cpu Riscv Rv32i Verilog Systemverilog Fpga Asic risc-v Assembler fpga-soc asic-design Axi4 axi4-protocol crossbar
Source Code
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airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
risc-v Riscv Fpga Verilog Embedded Systems AI Asic smart-sensors asil functional-safety Safety Security
Source Code
airisc.de
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friscv airisc_core_complex
1 1
14 70
- -
8.4 4.8
2 months ago 6 months ago
Coq Verilog
MIT License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

friscv

Posts with mentions or reviews of friscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

airisc_core_complex

Posts with mentions or reviews of airisc_core_complex. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-10.

What are some alternatives?

When comparing friscv and airisc_core_complex you can also consider the following projects:

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

riscv - RISC-V CPU Core (RV32IM)

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Hazard3 - 3-stage RV32IMACZb* processor with debug

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

biriscv - 32-bit Superscalar RISC-V CPU

cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

serv - SERV - The SErial RISC-V CPU

Cores-VeeR-EH1 - VeeR EH1 core

riscv-isa-manual - RISC-V Instruction Set Manual

friscv vs darkriscv airisc_core_complex vs riscv friscv vs ravenoc airisc_core_complex vs Hazard3 friscv vs scr1 airisc_core_complex vs biriscv friscv vs cheshire airisc_core_complex vs darkriscv friscv vs rp32 airisc_core_complex vs serv friscv vs Cores-VeeR-EH1 airisc_core_complex vs riscv-isa-manual