edalize VS zerosoc

Compare edalize vs zerosoc and see what are their differences.

edalize

An abstraction library for interfacing EDA tools (by olofk)
eda Fpga fossi Xilinx altera lattice yosys Synthesis Simulation Verilog Vhdl Systemverilog Verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
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zerosoc

Demo SoC for SiliconCompiler. (by siliconcompiler)
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edalize zerosoc
4 2
590 49
- -
7.3 7.2
7 days ago about 1 month ago
Python SystemVerilog
BSD 2-clause "Simplified" License -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

edalize

Posts with mentions or reviews of edalize. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.
  • Dropping EDA-GUI's 101
    1 project | /r/FPGA | 17 Feb 2023
    Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
  • Introduction to FPGAs
    9 projects | news.ycombinator.com | 6 Feb 2023
    Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
    This reminds me very much of edalize[1], which does something very similar.

    [1]: https://github.com/olofk/edalize

  • Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
    3 projects | /r/RISCV | 24 Sep 2021

zerosoc

Posts with mentions or reviews of zerosoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-12-07.

What are some alternatives?

When comparing edalize and zerosoc you can also consider the following projects:

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

apio - :seedling: Open source ecosystem for open FPGA boards

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

myhdl - The MyHDL development repository

icestudio - :snowflake: Visual editor for open FPGA boards

gssi - Stuff I worked on while at GSSI (L'Aquila, Italy)

rggen - Code generation tool for control and status registers

chisel - Chisel: A Modern Hardware Design Language

edalize vs fusesoc zerosoc vs openlane edalize vs skywater-pdk zerosoc vs skywater-pdk edalize vs apio zerosoc vs freepdk-45nm edalize vs freepdk-45nm zerosoc vs myhdl edalize vs icestudio zerosoc vs gssi edalize vs rggen zerosoc vs chisel