edalize VS tinyTPU

Compare edalize vs tinyTPU and see what are their differences.

tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT. (by jofrfu)
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edalize tinyTPU
4 1
579 326
- -
7.3 10.0
20 days ago about 5 years ago
Python VHDL
BSD 2-clause "Simplified" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

edalize

Posts with mentions or reviews of edalize. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.

tinyTPU

Posts with mentions or reviews of tinyTPU. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.

What are some alternatives?

When comparing edalize and tinyTPU you can also consider the following projects:

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

apio - :seedling: Open source ecosystem for open FPGA boards

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

icestudio - :snowflake: Visual editor for open FPGA boards

rggen - Code generation tool for control and status registers

sphinx-vhdl

opentitan - OpenTitan: Open source silicon root of trust

hdl_checker - Repurposing existing HDL tools to help writing better code

serv - SERV - The SErial RISC-V CPU

f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.