edalize
hdl_checker
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| edalize | hdl_checker | |
|---|---|---|
| 4 | 4 | |
| 587 | 181 | |
| - | - | |
| 7.3 | 0.0 | |
| 7 days ago | 4 months ago | |
| Python | Python | |
| BSD 2-clause "Simplified" License | GNU General Public License v3.0 only |
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edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
completor.vim - Async completion framework made ease.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
rust_hdl
apio - :seedling: Open source ecosystem for open FPGA boards
veridian - A SystemVerilog Language Server
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
icestudio - :snowflake: Visual editor for open FPGA boards
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
rggen - Code generation tool for control and status registers
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!