durexforth VS swapforth

Compare durexforth vs swapforth and see what are their differences.


Modern C64 Forth (by jkotlinski)


Swapforth is a cross-platform ANS Forth (by jamesbowman)
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durexforth swapforth
5 4
201 255
- -
8.3 0.0
5 days ago 7 months ago
Forth Forth
GNU General Public License v3.0 or later BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of durexforth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-02-17.


Posts with mentions or reviews of swapforth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-25.
  • FPGAs for interpreted programming languages?
    2 projects | /r/FPGA | 25 Nov 2022
  • How many LUT for an 8 bit CPU?
    2 projects | /r/FPGA | 11 Nov 2022
    Thanks! Found the port of this to the board I want :) https://github.com/jamesbowman/swapforth/tree/master/j1a
  • The RISC Deprogrammer
    2 projects | news.ycombinator.com | 28 Oct 2022
    It's a standard thing to do in EE curricula; you normally do it in a one-semester class, and there are literally thousands of open-source synthesizable CPU cores on GitHub now.

    To take two examples to show that designing a CPU is less work than writing a novel:

    - Chuck Thacker's "A Tiny Computer", fairly similar to the Nova, is a page and a half of synthesizable Verilog; it runs at 66 MHz in 200 LUTs of a Virtex-5: https://www.cl.cam.ac.uk/~swm11/examples/bluespec/Tiny3/Thac...

    - James Bowman's J1A is more like Chuck Moore's MuP21 and is about three pages of synthesizable Verilog: https://github.com/jamesbowman/swapforth/blob/master/j1a/ver... and https://github.com/jamesbowman/swapforth/blob/master/j1a/ver.... You can build it with Claire Wolf's iCEStorm (yosys, etc.) and run it on any but Lattice's tiniest FPGAs; it takes up 1162 4-input LUTs.

    I haven't quite done it myself. Last time I played https://nandgame.com/ it took me a couple of hours to play through the hardware design levels. But that's not really "design" in the sense of defining the instruction set (which is also kind of Nova-like), thinking through state machine design, and trying different pipeline depths; you're mostly just doing the kind of logic minimization exercises you'd normally delegate to yosys.

    In https://github.com/kragen/calculusvaporis I designed a CPU instruction set, wrote a simulator for it, wrote and tested some simple programs, designed a CPU at the RTL level, and sketched out gate-level logic designs to get an estimate of how big it would be. But I haven't simulated the RTL to verify it, written it down in an HDL, or breadboarded the circuit, so I'm reluctant to say that this qualifies as "designing a single CPU" either.

What are some alternatives?

When comparing durexforth and swapforth you can also consider the following projects:

zeptoforth - A not-so-small Forth for Cortex-M

arkam - A Simple Stack VM and Forth

factor - Factor programming language

jonesforth - Mirror of JONESFORTH

gforth - Gforth mirror on GitHub (original is on Savannah)

subleq - 16-bit SUBLEQ CPU running eForth - just for fun

stoneknifeforth - a tiny self-hosted Forth implementation

elfort - A Forth metacompiler that directly emits an executable binary for x86-64 Linux written in Arkam

lbForth - Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

gforth-raylib - Raylib 3.5 bindings for Gforth. The name is backwards for obvious reasons.