darkriscv VS riscv

Compare darkriscv vs riscv and see what are their differences.

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
Riscv processor-design Rv32i rv32e Verilog risc-v Fpga Rtl softcore Core Processor Cpu
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riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
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darkriscv riscv
3 2
1,873 1,040
2.3% -
6.8 1.8
2 months ago over 2 years ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

darkriscv

Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing darkriscv and riscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

zipcpu - A small, light weight, RISC CPU soft core

Cores-VeeR-EH1 - VeeR EH1 core

friscv - RISCV CPU implementation in SystemVerilog

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

uhd - The USRP™ Hardware Driver Repository

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

riscv vs biriscv darkriscv vs biriscv darkriscv vs XiangShan riscv vs openlane darkriscv vs VexRiscv riscv vs zipcpu darkriscv vs Cores-VeeR-EH1 darkriscv vs friscv riscv vs Toast-RV32i darkriscv vs meta-riscv riscv vs uhd darkriscv vs f4pga-examples