darkriscv
riscv
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| darkriscv | riscv | |
|---|---|---|
| 3 | 1 | |
| 1,630 | 742 | |
| 1.2% | - | |
| 2.8 | 1.0 | |
| 5 months ago | over 1 year ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
riscv
We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Cores-VeeR-EH1 - VeeR EH1 core
zipcpu - A small, light weight, RISC CPU soft core
friscv - RISCV CPU implementation in SystemVerilog
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog