cva6
ara
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cva6 | ara | |
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10 | 5 | |
2,042 | 296 | |
4.7% | 4.7% | |
9.7 | 7.9 | |
about 18 hours ago | 16 days ago | |
Assembly | C | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cva6
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
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XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
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How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
ara
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
The PULP Ara is a 64-bit Vector Unit
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I’m not expert, but I guess it is worth to check out
It's not made very clear until the Conclusion section that they have provided an open source implementation of a RVV 1.0 vector unit, available at https://github.com/pulp-platform/ara : "The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core."
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
What are some alternatives?
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
litex - Build your hardware, easily!
verilator - Verilator open-source SystemVerilog simulator and lint system
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
litedram - Small footprint and configurable DRAM core
gd32vf103inator - Program the GD32VF103 using C, your favourite editor and make
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga_floorplanning - NTHU CS5160 FPGA結構及設計自動化 麥偉基 Final Project
simd_utils - A header only library implementing common mathematical functions using SIMD intrinsics
NutShell - RISC-V SoC designed by students in UCAS
hdcp