cva6
gd32vf103inator
Our great sponsors
cva6 | gd32vf103inator | |
---|---|---|
10 | 1 | |
2,042 | 44 | |
4.7% | - | |
9.7 | 0.0 | |
about 21 hours ago | 12 months ago | |
Assembly | C++ | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cva6
-
Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
-
Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
-
Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
-
XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
-
How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
gd32vf103inator
We haven't tracked posts mentioning gd32vf103inator yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
litex - Build your hardware, easily!
USBMidiKliK - A robust USB MIDI Arduino firmware, with a dual bootloader, based on the LUFA library
verilator - Verilator open-source SystemVerilog simulator and lint system
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
litedram - Small footprint and configurable DRAM core
risc-v-examples - RISC-V examples for GD32V, K210, and QEMU
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
fpga_floorplanning - NTHU CS5160 FPGA結構及設計自動化 麥偉基 Final Project
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
bl_iot_sdk - BL602 SDK (Pine64 fork)