corundum
satcat5
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corundum | satcat5 | |
---|---|---|
28 | 24 | |
1,433 | 349 | |
3.0% | 30.7% | |
9.4 | 3.8 | |
3 months ago | 30 days ago | |
Verilog | VHDL | |
GNU General Public License v3.0 or later | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
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corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
Github Link
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Develop Network driver in Linux
First place I recommend taking a look at is the Linux kernel source code itself. Try to find an existing driver that does something similar, and figure out what interfaces it uses, how it connects to the kernel and the rest of the network stack. This is basically what I did when I wrote the driver for corundum (https://github.com/corundum/corundum) - I spent many hours reading over the drivers for Mellanox and Intel NICs. But in my case I also had to make the actual NIC, not just the driver.
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SatCat5 version 2.1 update
How does this project compare to say corundum? Would yours also be compatible with something like hXDP running at the same time on the same FPGA?
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
100 Gbps capable NIC, intended for research in datacenter networking and in-network computing: https://github.com/corundum/corundum . Includes core logic, designs targeting multiple FPGA boards, Python-based simulation framework, kernel module, and some userspace software.
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(New Discussion) What are you working on right now?
I'm working on building my own 100 Gbps NIC (https://github.com/corundum/corundum)
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FPGA development live stream: 10G Ethernet on Intel Stratix 10 MX and DX
For various reasons, I need to port corundum to run on Intel Stratix 10 MX and DX. As part of this process, I need to bring up both the PCIe and Ethernet interfaces on both of the cards. Also, even though both devices are Stratix 10, they use different tiles (H-tile on the MX vs. E-tile and P-tile on the DX) so the interface and capabilities are actually rather different. So, next week I'll run through the bring-up of a 10 Gbps link on both of these FPGAs by building example designs for verilog-ethernet. This will include setting up the H-tile and E-tile for operation at 10 Gbps as well as some debugging with both signaltap and the quartus "system console". If you want to learn a bit about how Intel FPGAs are put together, how 10G Ethernet works at the physical layer, and some of the techniques for debugging high speed serial links, be sure to tune in.
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How do you manage your Vivado projects in git?
My current method is to not check in any generated code in the first place. I have makefiles that create the vivado project and then run vivado to generate the bit file. All IP is done with tcl scripts, which were copied-and-pasted from what the IP wizard does to create the IP. The makefile writes out a tcl script that adds all of the source files, constraints files, and tcl scripts to generate the IP, then uses vivado batch mode to run the tcl script. I used to check in xci files, but these are locked to specific versions of vivado and as such are more annoying to work with; using TCL to create the IP has been significantly lower maintenance. See https://github.com/corundum/corundum/tree/master/fpga/mqnic for a bunch of different designs that use this same setup. It currently uses project mode so I can build from either the command line or from the GUI, but this would probably not be terribly difficult to change down the road if necessary.
satcat5
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Show HN: SatCat5, the open-source FPGA Ethernet switch
Hi!
I'm one of the engineers working with cubesat hardware and software integration, and I've been following this project since 2023 because I agree that standardizing over Ethernet over (twisted pair, UART, single pair, etc...) will solve a lot of integration pain from all of the DIY protocols that the cubesat/smallsat community uses
Some thoughts:
- You actually have a publicly available ICD at https://github.com/the-aerospace-corporation/satcat5/tree/ma... , please publicize this more in the readme! You're a very rare exception in a world of contact us and sign an NDA first and commercial in confidence ICDs, which is great, and leads me to my next point:
- Compared to HTTP API documentation, space ICDs sucks. One of the ICDs that I have put its protocol documentation as screenshots instead of copy pasteable text. Of course ICDs sucks because you won't know its quality until you buy it... Anyway standardizing on ethernet for transport layer give you all the tooling at 99% of the world's computer use, and it might be a first step in making a OpenAPI / Swagger type tool but for space protocols
- Any plans for 10base-T1S single pair ethernet? Our 6U cubesats barely have enough power to run its payload computers, let alone a FPGA based switch. But in a way a switched star network can be more reliable than a multidrop bus, as you can isolate babbling idiot nodes, and filter out accidental/intentional MAC/IP address spoofing
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
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Looking for a GitHub repo which contains unit tests
Here's a C++ example using Catch.
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Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
Cross-platform support for RMII and RGMII.
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1G Ethernet Using SGMII PHY
SatCat5 includes an open source SGMII MAC using LVDS GPIO on 7-Series FPGAs. Please note since of the platform-specific logic will need some adaptation for Ultrascale+.
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Ethernet on FPGA
Here's an RMII interface core.
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SatCat5 version 2.1 update
The SatCat5 team just posted version 2.1 to GitHub.
- Any recommendations for an RTL "standard library"?
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
SpinalHDL - Scala based HDL
litex - Build your hardware, easily!
surf - A huge VHDL library for FPGA development
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
hls4ml - Machine learning on FPGAs using HLS
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)