corundum VS SBusFPGA

Compare corundum vs SBusFPGA and see what are their differences.

corundum

Open source FPGA-based NIC and platform for in-network compute (by corundum)

SBusFPGA

Stuff to put a FPGA in a SBus system (SPARCstation) (by rdolbeau)
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corundum SBusFPGA
28 5
1,433 43
3.0% -
9.4 5.6
3 months ago 6 months ago
Verilog Python
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

corundum

Posts with mentions or reviews of corundum. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2024-03-27.
  • FuryGpu – Custom PCIe FPGA GPU
    15 projects | news.ycombinator.com | 27 Mar 2024
    The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
  • Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
    3 projects | /r/FPGA | 28 Nov 2022
  • Open source projects?
    4 projects | /r/FPGA | 21 Mar 2022
    Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
    4 projects | /r/FPGA | 21 Mar 2022
    Github Link
  • Develop Network driver in Linux
    2 projects | /r/linuxquestions | 19 Dec 2021
    First place I recommend taking a look at is the Linux kernel source code itself. Try to find an existing driver that does something similar, and figure out what interfaces it uses, how it connects to the kernel and the rest of the network stack. This is basically what I did when I wrote the driver for corundum (https://github.com/corundum/corundum) - I spent many hours reading over the drivers for Mellanox and Intel NICs. But in my case I also had to make the actual NIC, not just the driver.
  • SatCat5 version 2.1 update
    2 projects | /r/FPGA | 4 Dec 2021
    How does this project compare to say corundum? Would yours also be compatible with something like hXDP running at the same time on the same FPGA?
  • Share some github FPGA projects (bonus if they include C++, Python, or other files)
    15 projects | /r/FPGA | 14 Sep 2021
    100 Gbps capable NIC, intended for research in datacenter networking and in-network computing: https://github.com/corundum/corundum . Includes core logic, designs targeting multiple FPGA boards, Python-based simulation framework, kernel module, and some userspace software.
  • (New Discussion) What are you working on right now?
    13 projects | /r/archlinux | 24 Aug 2021
    I'm working on building my own 100 Gbps NIC (https://github.com/corundum/corundum)
  • FPGA development live stream: 10G Ethernet on Intel Stratix 10 MX and DX
    2 projects | /r/FPGA | 6 May 2021
    For various reasons, I need to port corundum to run on Intel Stratix 10 MX and DX. As part of this process, I need to bring up both the PCIe and Ethernet interfaces on both of the cards. Also, even though both devices are Stratix 10, they use different tiles (H-tile on the MX vs. E-tile and P-tile on the DX) so the interface and capabilities are actually rather different. So, next week I'll run through the bring-up of a 10 Gbps link on both of these FPGAs by building example designs for verilog-ethernet. This will include setting up the H-tile and E-tile for operation at 10 Gbps as well as some debugging with both signaltap and the quartus "system console". If you want to learn a bit about how Intel FPGAs are put together, how 10G Ethernet works at the physical layer, and some of the techniques for debugging high speed serial links, be sure to tune in.
  • How do you manage your Vivado projects in git?
    2 projects | /r/FPGA | 22 Apr 2021
    My current method is to not check in any generated code in the first place. I have makefiles that create the vivado project and then run vivado to generate the bit file. All IP is done with tcl scripts, which were copied-and-pasted from what the IP wizard does to create the IP. The makefile writes out a tcl script that adds all of the source files, constraints files, and tcl scripts to generate the IP, then uses vivado batch mode to run the tcl script. I used to check in xci files, but these are locked to specific versions of vivado and as such are more annoying to work with; using TCL to create the IP has been significantly lower maintenance. See https://github.com/corundum/corundum/tree/master/fpga/mqnic for a bunch of different designs that use this same setup. It currently uses project mode so I can build from either the command line or from the GUI, but this would probably not be terribly difficult to change down the road if necessary.

SBusFPGA

Posts with mentions or reviews of SBusFPGA. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-31.

What are some alternatives?

When comparing corundum and SBusFPGA you can also consider the following projects:

verilog-ethernet - Verilog Ethernet components for FPGA implementation

rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.

NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.

SpinalHDL - Scala based HDL

xfcp - Extensible FPGA control platform

litex - Build your hardware, easily!

hls4ml - Machine learning on FPGAs using HLS

soft_riscv - Soft-core RISCV processor for RISCV 2018 competition

psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA

BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.