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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub
4 projects | /r/FPGA | 4 Apr 2022
I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.
3 projects | /r/FPGA | 7 Nov 2021
The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.
Designing a Low Latency 10G Ethernet Core
2 projects | /r/FPGA | 4 Jul 2023
The use of cocotb and pyuvm for verification
How is Python used in test automation in embedded systems?
2 projects | /r/embedded | 19 Apr 2023
For FPGA/HDL work, there's cocotb
5 projects | /r/FPGA | 15 Apr 2023
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.5 projects | /r/FPGA | 15 Apr 2023
Regarding testbenches, they are currently not supported in CoHDL, but you can use Cocotb or any other existing test framework to check the produced VHDL representation.
Trying to learn and work with FPGAs
4 projects | /r/FPGA | 12 Apr 2023
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
Error when running cocotb using cocotb-test
2 projects | /r/FPGA | 6 Jun 2022
The only cocotb-supported version of Verilator is 4.106 (see this). But I tried that and quickly ran into issues. I have commercial access to questa sim and the same modules and testbenches worked just fine with that.
3 projects | /r/FPGA | 7 Nov 2021
How to simulate Verilog designs REALLY quickly ?
4 projects | /r/FPGA | 7 Nov 2021
I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?
What is the relation between Python and FPGA?
2 projects | /r/FPGA | 21 Sep 2021
You need an actual test setup. Clone the repo, go to examples, and run make TOPLEVEL_LANG=vhdl SIM=ghdl and see what happens.
What is the canonical way to test and simulate Chisel gateware ?
3 projects | /r/chisel | 15 Sep 2021
CocoTB (Python): I like this python test library. It easy to use, lot's of library to test i2c, uart, wishbone, ... And ... it's Python it's easy ! You can use the simulator you want and even switch between several without big problems. But it's slow simulation even with Verilator (beta) as backend.
What are some alternatives?
cocotb-test - Unit testing for cocotb
amaranth - A modern hardware definition language and toolchain based on Python
chiselverify - A dynamic verification library for Chisel.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
SpinalHDL - Scala based HDL
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
chisel - Chisel: A Modern Hardware Design Language
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
hdl_checker - Repurposing existing HDL tools to help writing better code
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
verilog-ethernet - Verilog Ethernet components for FPGA implementation
circt - Circuit IR Compilers and Tools