cocotb
chiselverify
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cocotb | chiselverify | |
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28 | 1 | |
1,568 | 129 | |
3.1% | 3.1% | |
9.7 | 2.2 | |
2 days ago | 1 day ago | |
Python | Scala | |
BSD 3-clause "New" or "Revised" License | BSD 2-clause "Simplified" License |
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cocotb
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Designing a Low Latency 10G Ethernet Core
The use of cocotb and pyuvm for verification
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How is Python used in test automation in embedded systems?
For FPGA/HDL work, there's cocotb
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Introducing CoHDL
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
Regarding testbenches, they are currently not supported in CoHDL, but you can use Cocotb or any other existing test framework to check the produced VHDL representation.
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Trying to learn and work with FPGAs
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
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Error when running cocotb using cocotb-test
The only cocotb-supported version of Verilator is 4.106 (see this). But I tried that and quickly ran into issues. I have commercial access to questa sim and the same modules and testbenches worked just fine with that.
- Cocotb
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How to simulate Verilog designs REALLY quickly ?
I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?
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What is the relation between Python and FPGA?
You need an actual test setup. Clone the repo, go to examples, and run make TOPLEVEL_LANG=vhdl SIM=ghdl and see what happens.
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What is the canonical way to test and simulate Chisel gateware ?
CocoTB (Python): I like this python test library. It easy to use, lot's of library to test i2c, uart, wishbone, ... And ... it's Python it's easy ! You can use the simulator you want and even switch between several without big problems. But it's slow simulation even with Verilator (beta) as backend.
chiselverify
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Chisel/Firrtl Hardware Compiler Framework
Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories.
That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since all your testing infrastructure is setup for testing assembly code and that is "what we have always been doing".
In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested:
What are some alternatives?
cocotbext-axi - AXI interface modules for Cocotb
cocotb-test - Unit testing for cocotb
SpinalHDL - Scala based HDL
amaranth - A modern hardware definition language and toolchain based on Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
chisel - Chisel: A Modern Hardware Design Language
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
hdl_checker - Repurposing existing HDL tools to help writing better code
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
circt - Circuit IR Compilers and Tools