cocotb VS chiselverify

Compare cocotb vs chiselverify and see what are their differences.

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python (by cocotb)
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cocotb chiselverify
28 1
1,568 129
3.1% 3.1%
9.7 2.2
2 days ago 1 day ago
Python Scala
BSD 3-clause "New" or "Revised" License BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

cocotb

Posts with mentions or reviews of cocotb. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-07-04.
  • Designing a Low Latency 10G Ethernet Core
    2 projects | /r/FPGA | 4 Jul 2023
    The use of cocotb and pyuvm for verification
  • How is Python used in test automation in embedded systems?
    2 projects | /r/embedded | 19 Apr 2023
    For FPGA/HDL work, there's cocotb
  • Introducing CoHDL
    5 projects | /r/FPGA | 15 Apr 2023
    At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
    5 projects | /r/FPGA | 15 Apr 2023
    Regarding testbenches, they are currently not supported in CoHDL, but you can use Cocotb or any other existing test framework to check the produced VHDL representation.
  • Trying to learn and work with FPGAs
    4 projects | /r/FPGA | 12 Apr 2023
    On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
  • Error when running cocotb using cocotb-test
    2 projects | /r/FPGA | 6 Jun 2022
    The only cocotb-supported version of Verilator is 4.106 (see this). But I tried that and quickly ran into issues. I have commercial access to questa sim and the same modules and testbenches worked just fine with that.
  • Cocotb
    3 projects | /r/FPGA | 7 Nov 2021
  • How to simulate Verilog designs REALLY quickly ?
    4 projects | /r/FPGA | 7 Nov 2021
    I heard about Verilator but it is quite something to learn and I am not sure if its the proper tool for my needs. I have looked into cocotb, but it does not work really well on my side. Could you guys recommend me anything ?
  • What is the relation between Python and FPGA?
    2 projects | /r/FPGA | 21 Sep 2021
    You need an actual test setup. Clone the repo, go to examples, and run make TOPLEVEL_LANG=vhdl SIM=ghdl and see what happens.
  • What is the canonical way to test and simulate Chisel gateware ?
    3 projects | /r/chisel | 15 Sep 2021
    CocoTB (Python): I like this python test library. It easy to use, lot's of library to test i2c, uart, wishbone, ... And ... it's Python it's easy ! You can use the simulator you want and even switch between several without big problems. But it's slow simulation even with Verilator (beta) as backend.

chiselverify

Posts with mentions or reviews of chiselverify. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-07-05.
  • Chisel/Firrtl Hardware Compiler Framework
    8 projects | news.ycombinator.com | 5 Jul 2021
    Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories.

    That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since all your testing infrastructure is setup for testing assembly code and that is "what we have always been doing".

    In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested:

    - https://github.com/chiselverify/chiselverify

What are some alternatives?

When comparing cocotb and chiselverify you can also consider the following projects:

cocotbext-axi - AXI interface modules for Cocotb

cocotb-test - Unit testing for cocotb

SpinalHDL - Scala based HDL

amaranth - A modern hardware definition language and toolchain based on Python

teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

chisel - Chisel: A Modern Hardware Design Language

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

hdl_checker - Repurposing existing HDL tools to help writing better code

PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

circt - Circuit IR Compilers and Tools